1. Field of the Invention
Embodiments of the invention relate to a method for initializing and operating a flash memory file system and a computer-readable medium storing a program for executing the method. In particular, embodiments of the invention relate to a method for initializing and operating a flash memory file system that uses a wear-leveling technique and a computer-readable medium storing a program for executing the method.
This application claims priority to Korean Patent Application No. 10-2006-0030381, filed on Apr. 4, 2006, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Because flash memory has relatively high stability, has relatively high storage capacity, and is relatively inexpensive, flash memory is generally used in embedded systems (e.g., a system embedded in a mobile device) and operated in association with another memory device (e.g., a Static Random Access Memory (SRAM) device), wherein the other memory device (i.e., an external memory device) has a relatively small storage capacity. Flash memory has a file system that is different from that of other types of memory devices such as Random Access Memory (RAM) devices, and there are limitations on the usage and operation of flash memory.
FIG. 1 is a diagram illustrating a conventional flash memory file system (i.e., flash file system). The conventional flash memory file system includes logical blocks 11 for storing logical addresses, wherein a logical address may identify a specific file, physical blocks 13 for storing actual data, and a map 12 for storing the relationship between the logical blocks and the physical blocks. When a task request involving a data file is received from an application (i.e., a program), the conventional flash memory file system operates to determine the logical address of the data file and access physical blocks 13 through map 12. The task request for the data file may be a request for a read operation, a write operation, an update operation, or the like.
In a flash memory file system such as the one described above, when a file is revised or updated, the task is performed on the basis of an erase unit. That is, flash memory is typically made up of blocks that each have a size of about 128 KB, and flash memory operates such that, after information has been written to a certain location, a write operation writing new data to that location is performed only after the entire erase unit containing that location has been erased.
The lifespan of a flash memory device is determined by the number of erase cycles the device can withstand. The lifespan of a Single Level Cell (SLC) is about 100,000 erase cycles. That is, an SLC may fail after about 100,000 erase operations. Therefore, in order to maximally utilize flash memory, erase cycles must be evenly distributed over the entire area of the flash memory (i.e., the “storage area”). A wear-leveling technique implemented in software has generally been used so that, over many operations, all of the blocks of the flash memory are used relatively evenly for the storage of data rather than using a specific block(s) the flash memory relatively heavily in the storage of data.
Such a wear-leveling technique can be defined simply as a technique for varying the mapping between logical blocks 11 and physical blocks 13 (i.e., the physical locations) in the flash memory file system of FIG. 1. In accordance with the wear-leveling technique, when a request to write a data file is received, information about the number of times each physical block 13 has been erased is evaluated by scanning such information for all of physical blocks 13 sequentially, as shown in FIG. 2, or in another predefined manner. Further, when data of the data file is set to be written to a first physical block 13 that has reached a preset maximum number of erasures, a first logical block 11 corresponding to first physical block 13 is mapped to a second physical block 13 having a relatively small number of erasures, and the data is consequently stored in second physical block 13. Thus, the wear-leveling technique can be seen as an algorithm implemented such that the logical addresses of logical blocks 11 are not continuously mapped to the same physical locations (i.e., the same physical blocks 13), respectively.
However, as described above, the conventional wear-leveling technique must scan the number of erasures (i.e., information about the number of erasures) performed on each physical block 13. That is, the number of erasures must be scanned for all physical blocks 13. In order to perform such a scan task, the scan task must be assigned a task space in an external memory device (e.g., an SRAM device, etc.). When, as mentioned above, the external memory device has a relatively small storage capacity, performing the scan task on all of physical blocks 13 decreases the overall performance of the entire system. Of course, this problem may be overcome by increasing the storage capacity of the external memory device. However, because increasing the size of the external memory device in a conventional embedded system also increases the total cost of the system, increasing the size of the external memory device is not a favored solution to the problem. Another drawback of the conventional wear-leveling technique is that performing the scan task takes a relatively long time since the scan task is performed on all of physical blocks 13.